module tb_seqdec_22;
	reg err;
	reg InA;
	wire Out;

	testbench DUB(.InA(InA), .err(err), .Out(Out));

	initial
	begin
	  err=1'b0;
          #210
	  InA = 1'b0;
	  #100
	  InA = 1'b0;
	  #100
	  InA = 1'b1;
	  #100
	  InA = 1'b0;
	  #100
	  InA = 1'b0;
	  #100
	  InA = 1'b0;
	  #100
	  InA = 1'b1;
	  #100
	  InA = 1'b0;
	  #100
	  InA = 1'b0;
	  #100
	  InA = 1'b0;
	  #100
	  InA = 1'b1;
	  #100
	  InA = 1'b0;
	  #100
	  InA = 1'b0;
	  #100
	  InA = 1'b1;
	  #100
	  InA = 1'b0;
	  #100
	  InA = 1'b0;
	  #100
	  InA = 1'b0;
	  #100
	  InA = 1'b1;
	  #100
	  InA = 1'b0;
	 end

	 always@(Out)
	   begin
	     #10
	     $display("Out is %b", Out);
	     end
endmodule


